Materials for Advanced Packaging

Preface

Preface to the First Edition

Contents

Contributors

About the Authors

Chapter 1: 3D Integration Technologies: An Overview

1.1 Introduction

1.1.1 Motivation for 3D Integration

1.1.2 Technology Platforms for 3D Integration and Packaging

1.2 Major Key Enabling 3D Technologies and Materials

1.2.1 Typical 3D Integration Process Flows

1.2.2 Wafer Thinning and Dicing

1.2.3 Wafer and Chip Stacking

1.3 TSV Integration Scheme and Process

1.3.1 TSV Integration Scheme and Process

1.3.1.1 TSV Integration Scheme

1.3.1.2 TSV Process Flow

1.3.1.3 TSV Scaling

1.3.2 Alternative TSV Process Options

1.4 Potential Limitations to 3D System Integration

1.5 Major Applications of 3D Integration

1.6 3D Integration Perspectives

References

Chapter 2: Advanced Bonding/Joining Techniques

2.1 Adhesive Bonding Techniques

2.1.1 Adhesives in the Electronic Industries

2.1.1.1 Epoxy Resins

2.1.1.2 Silicone Resins

2.1.1.3 Polyimides

2.1.1.4 Acrylics

2.1.2 Applications of Adhesives in Electronics

2.1.2.1 Integrated Circuits

2.1.2.2 Flexible Circuit

2.1.2.3 Liquid Crystal Display

2.1.3 New Adhesives

2.1.3.1 Liquid Crystal Polymer (LCP)

2.1.3.2 SU 8 Adhesive Bonding

2.2 Lead-Free Soldering Processes

2.2.1 Basic Soldering Processes

2.2.2 The Fluxless Processes Dealing with Tin Oxides

2.2.3 Oxidation-Free Fluxless Soldering Technology

2.3 Bonding Processes Using Silver Indium System for High Temperature Applications

2.3.1 Silver-Indium Phase Diagram and Reactions at 180C

2.3.2 Si Chips Bonded to Ag/Cu Substrates Using Ag-In System

2.3.3 Bonding Silicon Chips to Aluminum Substrates Using Ag-In System Without Flux

2.3.4 The Strength of High Temperature Ag-In Joints Made Between Copper by Fluxless Low Temperature Processes

2.3.5 Thermal Cycling Reliability Study of Ag-In Joints Between Si Chips and Cu Substrates Made by Fluxless Processes

2.4 Solid-State Bonding Technology

2.4.1 Introduction to Solid-State Bonding

2.4.2 Fundamental Principle of Solid-State Bonding

2.4.3 The Quantum Solid-State Bonding Theory

2.4.4 Novel Ag-to-Cu Solid-State Bonding a.k.a Direct Bonding

2.4.5 Cu-to-Ag/Cu Solid-State Bonding

2.5 Silver Flip-Chip Interconnect Technology

2.5.1 10mum Silver Flip-Chip Joints Made by 250C Solid-State Bonding Process

References

Chapter 3: Advanced Chip-to-Substrate Connections

3.1 Introduction

3.1.1 ITRS Projections for Flip-Chip Connections

3.1.2 Electrical Modeling of I/O

3.1.2.1 Parasitic Inductance of Chip-to-Substrate I/O

3.1.2.2 Parasitic I/O Capacitance

3.1.2.3 Characteristic Impedance

3.1.3 Mechanical Modeling

3.2 Compliant Solder-Based I/O Structures

3.2.1 Peripheral-to-Flip-Chip Area Array Structures

3.2.2 Redistribution Using Area Array Solder I/O

3.3 Wafer-Scale Compliant I/O

3.4 Improved Mechanical Performance Solder-Capped Structures

3.5 Solder-Free Chip-to-Substrate Interconnects

3.5.1 Copper Interconnects

3.5.1.1 Thermal-Compression Bonding

3.5.1.2 Surface-Activated Bonding

3.5.1.3 All-Copper Chip-to-Substrate Pillar Interconnects

3.5.2 Electroplated Copper Column Arrays

3.5.3 Compliant Gold Bump Interconnects

3.5.4 Electroless NiB Interconnects

3.6 Future Needs and Solutions for Chip-to-Substrate Connections

3.6.1 Ultra-High Off-Chip Frequency and High Bandwidth Operation

3.6.1.1 Coaxial Interconnects

3.6.1.2 Electrical and Optical Interconnects

3.6.2 Microfluidic Interconnects for Thermal Management

References

Chapter 4: Advanced Wire Bonding Technology: Materials, Methods, and Testing

4.1 Introduction

4.2 Interconnection Requirements

4.3 Bonding Principles

4.3.1 Wire Bonding Types

4.3.2 Thermocompression Bonding

4.3.3 Ultrasonic Bonding

4.3.4 Thermosonic Bonding

4.3.5 Other Techniques

4.3.6 Machine Optimization

4.4 Copper Ball Bonding

4.5 Materials

4.5.1 Bonding Wire

4.5.2 Bond Pads

4.5.3 Gold Plating

4.5.3.1 Electroplated Gold

4.5.3.2 Electroless Autocatalytic Gold

4.5.4 Pad Cleaning

4.6 Testing

4.7 Quality Assurance

4.8 Reliability

4.8.1 Intermetallics

4.8.2 Cratering

4.9 Design (Wire Spacing, Loop Height)

4.10 Advanced Concepts

4.10.1 Fine Pitch

4.10.2 Soft Substrates

4.10.3 Higher Frequency Bonding

4.10.4 Stud Bumping

4.10.5 Extreme Temperature Environments

4.11 Summary

References

Chapter 5: Lead-Free Soldering

5.1 Main Stream Lead-Free Soldering Practice

5.1.1 Driver of Lead-Free Soldering

5.1.2 Prevailing Lead-Free Solder Alloys

5.1.3 Lead-Free Surface Finishes

5.2 Physical and Mechanical Properties of Solder Joints

5.2.1 Melting Behavior

5.2.2 Creep Behavior

5.3 Intermetallic Compounds (IMC)

5.3.1 Effect of IMC on Joint Strength

5.3.2 Effect of Cu Content in Solder Alloy on IMC Stability on Ni Metallization

5.3.3 Effect of Additives on IMC

5.3.4 Effect of Metallization and Alloy on IMC

5.3.5 Effect of Heat History on IMC

5.4 Microstructure Evolution

5.4.1 Grain Coarsening

5.4.2 Creep-Fatigue

5.5 Temperature Cycling Reliability

5.5.1 Effect of Cycling Condition and Alloy on Reliability

5.5.2 Effect of PCB Metallization on Reliability

5.5.3 Effect of Ag Content on Reliability

5.6 Fragility

5.6.1 Effect of Ag Content on Fragility

5.6.2 Effect of Dopant on Fragility

5.6.3 Effect of Thermal Cycling Aging and Metallization on Fragility

5.7 Electromigration

5.8 Tin Whisker

5.8.1 Tin Whisker Growth Mechanism

5.8.2 Effect of CTE Mismatch on Tin Whisker

5.8.3 Effect of CuSn IMC on Tin Whisker

5.8.4 Other Means of Alleviating Tin Whisker Formation

5.9 Trends and Status of Novel Lead-Free Solder Alloys

5.9.1 Low Temperature Solder Alloys

5.9.2 Low Cost High Reliability Solder Alloys

5.9.3 High Temperature High Reliability Solder Alloys

5.10 Summary

References

Chapter 6: Thin Die Fabrication and Applications to Wafer Level System Integration

6.1 Introduction

6.2 Temporary Bonding/De-bonding and Thin Wafer Handling

6.3 Wafer Thinning

6.3.1 Motivation for Wafer Thinning

6.3.2 Wafer Thinning Processes, Tools, and Associated Defects

6.3.2.1 Mechanical Thinning

General Processes

Backgrinding Tools, Mechanism, and Defects

6.3.2.2 Chemical Mechanical Polishing (CMP)

General Processes

6.3.2.3 Wet Etching

HNA as an Etchant

TMAH as an Etchant

6.3.2.4 Dry Etching

Si Etching by SF6/O2 Plasma

Other Plasma and Dry Silicon Etching Processes

Plasma Etching Key Performance Parameters and Defectivity

6.4 TSV Revealing, Backside Processes, and Dicing

6.4.1 TSV Revealing

6.4.2 Backside RDL and Bumping

6.4.3 Dicing and Isolation

6.4.3.1 Blade Dicing

6.4.3.2 Laser Ablation

6.4.3.3 Stealth Dicing by Laser

6.5 Thin Dies for Wafer Level System Integration

6.5.1 Integrated Fan-Out Wafer Level System Integration, InFO

6.5.2 Chip-on-Wafer-on-Substrate, CoWoS

6.5.3 Summary on WLSI

References

Chapter 7: Advanced Substrates: A Materials and Processing Perspective

7.1 Introduction

7.1.1 A Brief History: from PCBs to Substrates

7.2 Ceramic Substrates

7.3 Organic Substrates

7.3.1 2L PBGA Substrates

7.3.2 4L PBGA Substrates

7.3.3 6L PBGA Substrates

7.3.4 High Density Interconnect Substrates: HDI

7.3.4.1 2L Via in Pad (ViP) Substrates (2L HDI)

7.3.4.2 1+2+1 Substrates (4L HDI)

7.3.4.3 1+4+1 Substrates (6L HDI)

7.3.4.4 2+2+2 Substrates (6L HDI)

7.3.5 Single-Sided Substrates

7.3.6 Embedded Trace Substrates

7.3.7 Substrate-Less Packages Based on Substrate Technology

7.3.8 Coreless Substrates

7.4 Tape Ball Grid Array: TBGA

7.5 PBGA Substrate Trends

7.5.1 Low Cost Dielectrics

7.5.2 Low Cost Solder Masks

7.5.3 Thin Substrates, Thin Dielectrics

7.5.4 Low Expansion Dielectrics

7.5.5 Surface Finishes

7.5.5.1 Electroplated Nickel Gold

7.5.5.2 OSP and AFOP

7.5.5.3 ENEPIG and EPIG

Tin-Based Surface Finishes

Immersion Tin: iT

Electroplated Tin: eT and Binary Solders

Super Juffit

7.6 FCBGA Substrates

7.7 Specialty Substrates

7.7.1 RF Modules

7.7.2 High Performance Substrates with Low Dielectric Constant

7.7.3 Substrates with Embedded Components

7.7.3.1 Buried Passives Substrates

7.7.3.2 Embedded Die and Embedded Passives Substrates

7.7.3.3 Cavity Substrates

References

Trademarks

Chapter 8: Flip-Chip Underfill: Materials, Process, and Reliability

8.1 Introduction

8.2 Conventional Underfill Materials and Process

8.3 Reliability of Flip-Chip Underfill Packages

8.4 New Challenges to Underfill

8.5 No-Flow Underfill (NUF)

8.5.1 Approaches of Incorporating Silica Fillers into No-Flow Underfill

8.6 Molded Underfill

8.7 Wafer Level Underfill

8.8 Underfill for 3D Stacks

8.9 Nanocomposites Underfill

8.10 Summary

References

Chapter 9: New Development Trend of Epoxy Molding Compound for Encapsulating Semiconductor Chips

9.1 Introduction

9.2 Introduction to Epoxy Molding Compounds

9.2.1 Epoxy Resin

9.2.2 Hardener

9.2.3 Inorganic Filler

9.2.4 Silane-Coupling Agent

9.2.5 Flame Retardant

9.2.6 Other Additives

9.3 Beyond Transfer Molding

9.3.1 Granule Epoxy Molding Compound

9.3.2 Sheet Epoxy Molding Compound

9.4 Epoxy Molding Compound for Advanced Packages

9.4.1 Flip Chip Application

9.4.1.1 Filling Performance

9.4.1.2 Warpage Management

9.4.1.3 Bump Protection for SiP Application

9.4.2 Cu/Ag-Wire Application

9.4.2.1 Analysis of Wire Bonding Part After HAST

9.4.2.2 Corrosion Mechanism of Wire Bonds

9.4.2.3 HTSL Results for EMC

9.4.3 Development of EMCs for Premold L/F and Molded Substrate

9.4.3.1 Pre-mold L/F

9.4.3.2 Molded Substrate

9.4.4 WLP Application

9.4.4.1 EMC for FOWLP

9.4.5 High Temperature Application

9.4.5.1 Introduction

9.4.5.2 EMC Materials with High Heat Resistance

9.4.6 Study of Epoxy Molding Compound for Fingerprint Sensor

9.4.6.1 Introduction

9.4.6.2 Type of Fingerprint Sensor

9.4.6.3 Principle of Fingerprint Sensor

9.4.6.4 EMC for Fingerprint Sensor

9.5 Summary

References

Chapter 10: Electrically Conductive Adhesives (ECAs)

10.1 Introduction

10.2 Description of Anisotropically Conductive Adhesives

10.2.1 Overview

10.2.2 Adhesive Matrix

10.2.3 Conductive Fillers

10.2.3.1 Solid Metal Particles

10.2.3.2 Non-Metal Particles with Metal Coating

10.2.3.3 Metal Particles with Insulating Coating

10.2.3.4 Nanoparticles

10.2.3.5 Self-Aligned Magnetic Particles

10.2.3.6 Nanofiber/Solder

10.3 Flip Chip Applications Using Anisotropically Conductive Adhesives

10.3.1 ACA Flip Chip for Bumped Dies

10.3.1.1 Two Filler Systems

10.3.1.2 Coated Plastic Filler

10.3.1.3 Solder Filler Systems

10.3.1.4 Ni Filler

10.3.2 ACA Bumped Flip Chips on Glass Chip Carriers

10.3.2.1 Selective Tacky Adhesive Method

10.3.2.2 The MAPLE Method

10.3.3 ACA Bumped Flip Chips for High Frequency Applications

10.3.4 ACA for Unbumped Flip Chips

10.3.4.1 Gold-Coated Nickel Filler

10.3.4.2 Ni/Au-Coated Silver Filler

10.3.4.3 Metal Pillar ACF

10.3.5 ACAs for CSP and BGA Applications

10.3.5.1 Double-Layered ACF Film

10.3.5.2 Ceramic Chip Carriers vs. Organic Chip Carriers

10.3.6 Failure Mechanism

10.3.6.1 Oxidation of Non-Noble Metals

10.3.6.2 Loss of Compressive Force

10.4 Description of Isotropic Conductive Adhesives (ICAS)

10.4.1 Percolation Theory of Conduction

10.4.2 Adhesive Matrix

10.4.3 Conductive Fillers

10.4.3.1 Silver Particles

10.4.3.2 Silver-Coated Copper Particles

10.4.3.3 Low-Melt Fillers

10.4.3.4 Nanoparticles

Silver Nanowires

Carbon Nanotubes (CNTs)

Copper Nanoparticles

AgNPs/Reduced Graphene Oxide (rGO)

In Situ NanoAg-Coated Silver Flakes

10.5 Flip Chip Applications Using Isotropic Conductive Adhesives

10.5.1 Polymer Bump Flip Chip

10.5.2 Metal-Bumped Flip Chip Joints

10.5.3 ICA Process for Unbumped Chips

10.6 Surface Mount Applications

10.7 ICAs for CSP Applications

10.8 ICAs for Advanced Packaging Applications

10.8.1 Solar Cell

10.8.2 3D Stacking

10.8.3 Microspring

10.8.4 ICAs for Printed Circuit Board Applications

10.9 High-Frequency Performance of ICA Joints

10.10 Reliability of ICA Joints

10.11 Recent Advances on ICAS

10.11.1 Improvement of Electrical Conductivity

10.11.2 Eliminate Lubrication Layer

10.11.3 Increase Shrinkage

10.11.4 Transient Liquid Phase Fillers

10.11.4.1 Incorporation of Intrinsic Conducting Polymers

10.11.4.2 Polymer Resin Alloy

10.11.5 Improvement of Contact Resistance Stability

10.11.5.1 Causes for Resistance Increase

10.11.5.2 Approaches to Stabilize Contact Resistance

Reduce Moisture Absorption

Use of Corrosion Inhibitors

Use of Oxygen Scavengers

Sharp-Edge Filler Particles

10.11.6 Improvement of Impact Performance

References

Chapter 11: Die Attach Adhesives and Films

11.1 Die Attach Materials

11.1.1 Trends in Electronic Packaging

11.1.2 Trends in Die Attach Materials

11.1.3 Demands on Die Attach Materials

11.1.4 Die Attach Paste

11.1.5 Adhesive Tape for LOC Package

11.1.6 Die Attach Film

11.1.7 The Future of Advanced Die Attach Film

11.1.7.1 Die Attach Film for Advanced BGA/CSP

11.1.7.2 Dicing/Die Attach Dual Functioning Film

11.1.7.3 Die Attach Film for Multi-Layered Packaging Process

11.2 Development of Die Attach Film with High Performance for Package Cracking Resistance and Advanced Package

11.2.1 Introduction

11.2.1.1 Technical Issues of Silver Paste

11.2.1.2 Package Crack

11.2.1.3 Advanced Packages

11.2.2 Design of Base Resin for Die Attach Film

11.2.3 Die Attach Film for Package Crack Resistance

11.2.3.1 Water Absorption of Base Resin

11.2.3.2 Peel Strength

11.2.3.3 Package Cracking Resistance

11.2.4 Die Attach Film for Advanced Package

11.2.4.1 Low Tg and Low Water Absorptivity of Polyimide Base Resin

11.2.4.2 Low Stress (Silicon Chip Warpage)

11.2.4.3 Low Attaching Temperature

11.2.4.4 Properties of Die Attach Film

11.3 Development of Die-Bonding Film by Nano-Structure Control and Mathematical Optimization

11.3.1 Material System Based on Reaction-Induced Phase Decomposition

11.3.2 Material Design System Based on Reaction-Induced Phase Decomposition

11.4 Technologies for Next-Generation Packages

References

Chapter 12: Thermal Interface Materials

12.1 What Is Thermal Interface Resistance?

12.2 Recent Development in Thermal Interface Modeling

12.2.1 Model to Predict Thermal Conductivity (kTIM)

12.2.2 Rheological Model to Predict TIM Bondline Thickness (BLT)

12.2.3 Effect of Particle Volume Fraction on Bulk TIM Thermal Resistance

12.2.4 Model to Predict Thermal Contact Resistance (Rc)

12.3 Reliability Consideration for Polymeric TIMs

12.4 Solder Alloy-Based TIMs

12.5 Nanotechnology-Based TIMs

12.6 Characterization of TIM Thermal Performance

12.7 Future Directions

References

Chapter 13: Embedded Passives

13.1 Introduction

13.1.1 Passives in Power Modules

13.2 Embedded Inductors

13.2.1 Introduction

13.2.1.1 Limitations of Discrete Inductors and Air Core Spiral Inductors

13.2.1.2 Advantages of Magnetic Inductors as Embedded Inductors

13.2.1.3 Inductor Designs

13.2.1.4 Requirements and Survey for the Magnetic Core Materials

13.2.2 Modeling and Design Considerations of Magnetic Inductors

13.2.2.1 Inductance

13.2.2.2 Resistance

13.2.2.3 Quality Factor

13.2.2.4 Saturation Current

13.2.3 Embedded On-package and On-chip Inductors: Experiments and Analyses

13.2.3.1 On-chip Inductor Results

13.2.3.2 On-package Inductor Results

13.2.3.3 Fundamental Trade-Offs of Magnetic Inductors

13.2.4 Future Directions of the Embedded Magnetic Inductors

13.2.4.1 Potential Applications for the Integrated Magnetic Inductors

13.2.4.2 Survey of Inductor Works in Literature

13.2.4.3 Challenges

13.2.4.4 Direction for Embedded Inductors

13.3 Capacitor Technologies

13.3.1 Discrete Capacitors

13.3.1.1 MLCC

13.3.1.2 Electrolytic Capacitors with Sintered Porous Ta and Etched Al Foils

13.3.2 Integrated Capacitors

13.3.2.1 Thin-Film Capacitors

13.3.2.2 Trench Capacitors

13.3.3 Emerging Nanoscale Capacitors

13.3.4 Future of Power Capacitors

13.4 Embedded Resistors

13.4.1 Introduction

13.4.2 Fundamental of Resistors

13.4.3 Design, Materials, and Processing Technologies

13.4.3.1 Design

13.4.3.2 Materials and Processes

13.4.4 Challenges and Solutions with Embedded Resistors

13.4.4.1 Yield

13.4.4.2 High Temperature and Humidity Stability

13.4.4.3 Precision Patterning with Laser Trimming

13.4.4.4 Precision Patterning with Dry Etching

13.5 Conclusions

References

Chapter 14: Advanced Bonding Technology Based on Nano- and Micro-metal Pastes

14.1 Introduction

14.2 Silver Pastes

14.2.1 From Micro-Ag Paste to Nano-Ag Pastes

14.2.2 Performance of Joints Based on Nano-Ag Pastes

14.2.2.1 Sintering Pressure in Nano-Ag Pastes

14.2.2.2 Sintering Temperature and Time in Nano-Ag Pastes

14.2.2.3 Heating Rate in Nano-Ag Pastes

14.2.3 From Nano-Ag Pastes to Hybrid Silver Pastes

14.2.3.1 The Fabrication Methods of Hybrid Ag Pastes

14.2.3.2 The Joint Performance and Reliability of Hybrid Ag Pastes

14.3 Copper Pastes

14.3.1 Synthesis of Cu Pastes

14.3.2 Anti-oxidation Methods for the Sintering of Cu Pastes

14.3.3 The Joint Performance of Cu Pastes

14.4 Other Bonding Techniques

14.5 Conclusion

References

Chapter 15: Wafer Level Chip Scale Packaging

15.1 Introduction

15.2 Definition of Wafer Level Chip Size Packaging

15.3 Materials and Processes for Bumping and Redistribution Technology

15.3.1 Metals for Wafer Bumping

15.3.1.1 Under Bump Metallization

15.3.1.2 Bumping Technologies

15.3.1.3 Bump Metallurgy

15.3.1.4 Plating of Alloys

15.3.1.5 Yield and Reliability

15.3.2 Photoresists for Wafer Bumping

15.3.3 Processing of Photoresist and Photopolymers

15.3.4 Polymers for Redistribution Layers (RDL)

15.3.4.1 Chemistry of Polymers for RDL

15.3.4.2 Adhesion and Copper Diffusion into Polymers

15.4 Materials for Integrated Passives into WLP

15.5 Influence of the Polymer to the Reliability of WLP

15.6 Conclusion

References

Chapter 16: Microelectromechanical Systems and Packaging

16.1 Introduction

16.2 Packaging of MEMS

16.3 MEMS for Packaging

16.4 Packaging for MEMS

16.5 Opportunities and Major Challenges

16.6 Conclusions

References

Chapter 17: LED Die Bonding

17.1 LED Chips and Packaging

17.1.1 Introduction

17.1.2 LED Chips

17.1.3 Packages and Packaging

17.1.4 Packaging Materials

17.2 Die Bonding Materials

17.2.1 Material Requirement

17.2.2 Types of Die Bonding Materials

17.2.2.1 Adhesives

Silver DAAs

Optical DAAs for Low- and Mid-Power LEDs

Optical DAAs for High-Power LEDs

17.2.2.2 Adhesive Films

17.2.2.3 Solder Materials for LED Die Bonding

17.2.2.4 Low-Temperature Sintering Silver Pastes

17.3 Packaging and Die Bonding Materials

17.3.1 SMD LEDs

17.3.1.1 Optical Role of DAAs for Low- and Mid-Power LEDs

17.3.1.2 Nonuniformity in SMD LEDs

Materials Parameters

Process Parameters

Package Parameters

17.3.1.3 Optimal SMD LEDs Design

Guidance of OC-DAAs and WDAAs Design

Optimal Selection of Packages

Optimal Packaging Processes and Parameters

17.3.2 COB LEDs

17.3.3 FC LEDs and CSP

17.3.4 Wafer-Level CSP LEDs

References

Chapter 18: Medical Electronics Design, Manufacturing, and Reliability

18.1 Introduction

18.1.1 Review of Medical Electronic Products Classification

18.1.2 Class I Medical Devices

18.1.3 Class II Medical Devices

18.1.4 Class III Medical Devices

18.2 Key Drivers for Growth in Medical Electronics

18.2.1 Aging Population

18.2.2 Demographic Shift Toward Tech-Competent User Base

18.2.3 Target Market Moving from Treatment to Detection and Prevention

18.2.4 Availability of Advanced Electrical Content

18.3 Design Concepts and Enabling Technologies

18.3.1 Low Power Consumption

18.3.2 Miniaturization

18.3.3 Growth and Standardization of Wireless

18.3.4 Sensors, Accelerometers, and Medical Monitoring

18.3.5 Advanced Wafer Fabrication Availability

18.3.6 Silicon Integration and Electronic Packaging

18.4 Implantable Medical Electronics Design and Reliability

18.4.1 Implantable Medical Electronic Applications

18.4.2 Development Process

18.4.3 Environmental Conditions and Constraints

18.4.4 Manufacturing Stresses

18.4.5 Shipping and Storage

18.4.6 Implant Conditions

18.4.7 Longevity Requirements

18.4.8 Reliability Requirements

18.4.9 System Level Failure Modes

18.4.10 Commonly Encountered Failure Mechanisms

18.5 Qualification

18.5.1 Qualification Overview

18.5.2 Qualification, Verification, and Validation

18.5.3 Manufacturing Process Controls

18.5.4 Component and Material Qualification

18.5.5 Electronic Module Qualification

18.5.6 Finished Device Qualification

18.5.7 Supplier Controls

18.6 Manufacturing and Process Development

18.6.1 Manufacturing Process and Materials

18.6.2 Beyond 6-Sigma: Developing Transfer Functions

18.6.3 Change Management

18.7 Implantable Medical Device Challenges

18.7.1 CMOS Scaling

18.7.2 Lead-Free Requirements Impact

18.7.3 Increasing Device Complexity

18.7.4 External System Interfaces

18.7.5 Qualification Strategies for the Future

References

Chapter 19: Flexible and Printed Electronics

19.1 Introduction

19.2 Flexible Thin-Film Transistor Backplane Technology

19.2.1 Hydrogenated Amorphous Silicon TFTs

19.2.2 Low-Temperature Polycrystalline Silicon TFTs

19.2.3 Oxide TFTs

19.2.4 Organic TFTs

19.2.5 Fabrication of Flexible TFTs

19.2.5.1 Lamination-Debonding Approach

19.2.5.2 Coat (Deposit)-Release Approach

19.2.5.3 Transfer Approach

19.3 Printing Technology for Flexible Electronics Applications

19.3.1 Printing Technologies

19.3.1.1 Gravure, Gravure-Offset, Flexographic, and Rotary Screen Printing

19.3.1.2 Microcontact Printing, Nanoimprint, and Transfer Printing

19.3.1.3 Slot-Die and Inkjet Printing

19.3.2 Subtractive and Additive Printing Processes

19.3.2.1 Subtractive Printing Process

19.3.2.2 Additive Printing Process

19.4 Outlook

References

Chapter 20: Silicon Solar Cell Metallization Pastes

20.1 Silicon Solar Cells

20.1.1 Crystalline Silicon Solar Cells

20.1.2 Development Trend

20.2 Metallization

20.2.1 Front-Side Metallization

20.2.1.1 Requirement

20.2.1.2 Conventional Silver Pastes and Application Methods

20.2.1.3 Novel Silver Pastes with Silver Nanoparticles for Screen Printing

20.2.1.4 Glass Frits and Nano-Frits

20.2.1.5 Novel Methods for Formation of Silver Electrodes

20.2.1.6 Copper/Nickel for Front Metallization

20.2.1.7 Screen-Printable Low-Temperature Copper Pastes for Front Busbars

20.2.2 Back-Side Metallization

20.2.2.1 Aluminum and Aluminum/Silver Pastes for Back Surface Field

20.2.2.2 Local BSF for Passivated Emitter and Rear Solar Cells

20.2.3 Future of Metallization Materials and Techniques

20.3 Solar Cell Modules

20.3.1 Components of Solar Cell Modules

20.3.2 Manufacturing Process

20.3.3 Development Trends

References

Chapter 21: Nano-metal-Assisted Chemical Etching for Fabricating Semiconductor and Optoelectronic Devices

21.1 Introduction

21.1.1 Challenges of Top-Down Nanofabrication

21.2 Background on Metal-Assisted Chemical Etching (MacEtch)

21.2.1 History of MacEtch

21.2.2 Chemistry

21.2.3 Metal Catalysts

21.2.4 Etchant

21.2.5 Crystallographic Dependencies

21.2.6 Microporous Silicon

21.3 Fabrication with MacEtch

21.3.1 Pores and Nanowires

21.3.2 Channels

21.3.3 3D Fabrication

21.3.4 Helical/Spiral Structures

21.3.5 Electroless Filling MacEtch Templates

21.4 Devices and Applications of MacEtch

21.4.1 X-Ray Diffractive Optics

21.4.2 Thru-Silicon-Via (TSV)

21.4.3 MEMS

21.4.4 Photovoltaics

21.5 Practical Processing Considerations

21.5.1 Catalyst and Process Design

21.5.2 Etch Stop

21.5.3 Fluid Flow Induced Motion and Pre-etch HF Dips

21.5.4 Adhesion Layer Thickness

21.5.5 Top Layer of Catalyst Stack

21.5.6 Catalyst Cleanliness and Etchant Stability

References

Chapter 22: Characterization of Copper Diffusion in Through Silicon Vias

22.1 Cu Diffusion in Through Silicon Vias

22.1.1 Barrier Materials for Preventing Cu Diffusion

22.1.2 Evaluation of Barrier Layer Stability

22.1.3 SIMS Depth Profiling of Cu Diffusion

22.2 Effect of Interfacial Multilayer

22.2.1 Effect of Insulation Layer

22.2.2 Effect of Si Surface Roughness

22.2.3 Effects of Barrier Layer and Cu Source Layer

22.3 Phase Transition in Thermal Annealing

22.4 Factor Rank for Cu Diffusion

22.4.1 DOE for Rank Analysis

22.4.2 Diffusion Depth versus Annealing Time

22.4.3 Rank Analysis of Different Layers

References

Index